FUNDAMENTALS OF VLSI DESIGN BEE515D

Picsart 25 08 10 16 02 45 203

FUNDAMENTALS OF VLSI DESIGN BEE515D

Course Code: BEE515D

Credits: 03

CIE Marks: 50

SEE Marks: 50

Total Marks: 100

Exam Hours: 03

Total Hours of Pedagogy: 40H

Teaching Hours/Weeks: [L:T:P:S] 3:0:0:0

Moore’s law, speed power performance, nMOS fabrication, CMOS fabrication: n-well, p-well processes, BiCMOS, Comparison of bipolar and CMOS.

Basic Electrical Properties of MOS And BiCMOS Circuits: Drain to source current versus voltage characteristics, threshold voltage, transconductance.

Basic Electrical Properties of MOS And BiCMOS Circuits: nMOS inverter, Determination of pull up to pull downratio, nMOS inverter driven through one or more pass transistors, alternative forms of pull up, CMOS inverter,BiCMOS inverters, latch up.

Basic Circuit Concepts: Sheet resistance, area capacitance calculation, Delay unit, inverter delay, estimation ofCMOS inverter delay, driving of large capacitance loads, super buffers, BiCMOS drivers.

MOS and BiCMOS Circuit Design Processes: MOS layers, stick diagrams, nMOS design style, CMOS design style, design rules and layout, λ – based design.

Scaling of MOS Circuits: scaling factors for device parameters, limitations of scaling.

Subsystem Design and Layout-1: Switch logic pass transistor, Gate logic inverter, NAND gates, NOR gates,pseudo nMOS, Dynamic CMOS, example of structured design, Parity generator, Bus arbitration, multiplexers, logicfunction block, code converter.

Subsystem Design and Layout-2: Clocked sequential circuits, dynamic shift registers, bus lines, subsystem designprocesses, General considerations, 4-bit arithmetic processes, 4-bit shifter.

Design Process-Computational Elements: Regularity, design of ALU subsystem, ALU using adders, carry lookahead adders, Multipliers, serial parallel multipliers, Braun array, Bough – Wooley multiplier.

Memory, Registerand Aspects of Timing: Three Transistor Dynamic RAM cell, Dynamic memory cell, Pseudo- Static RAM, JK Flipflop,D Flip-flop circuits, RAM arrays, practical aspects and testability: Some thoughts of performance, optimizationand CAD tools for design and simulation.

Important questions

guest
0 Comments
Inline Feedbacks
View all comments