Digital System Design using Verilog BEC302

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Digital System Design using Verilog BEC302

Course Code: BEC302

Credits: 04

CIE Marks: 50

SEE Marks: 50

Total Marks: 100

Exam Hours: 03

Total Hours of Pedagogy: 40H

Teaching Hours/Weeks: [L:T:P:S] 3:0:2:0

Principles of Combinational Logic: Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps-up to 4 variables, QuineMcCluskey Minimization Technique. Quine-McCluskey using Don’t CareTerms

Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices(PLDs)

Flip-Flops and its Applications: The Master-Slave Flip-flops(Pulse-Triggered flip-flops):SR flipflops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters, Synchronous Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using clocked T, J K, D and SR flip-flops.

Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of Description.

Verilog Data flow description: Highlights of Data flow description, Structure of Data flow description.

Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential Statements, Loop Statements, Verilog Behavioral Description of Multiplexers

Verilog Structural description: Highlights of Structural description, Organization of structural description, Structural description of ripple carry adder.

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