FPGA Based System design Using Verilog BEC613D

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FPGA Based System design Using Verilog BEC613D

Course Code: BEC613D

Credits: 03

CIE Marks: 50

SEE Marks: 50

Total Marks: 100

Exam Hours: 03

Total Hours of Pedagogy: 40H

Teaching Hours/Weeks: [L:T:P:S] 3:0:0:0

Introduction to Programmable Logic Devices: Hazards in Combinational Circuits, Brief overview of Programmable Logic Devices, Simple Programmable Logic Devices (SPLDs) Complex Programmable Logic devices (CPLDs), Field-Programmable Gate Arrays (FPGAs)

Advanced Digital Design Examples: BCD to 7-Segment Display Decoder, BCD Adder, Traffic Light controller, Synchronization and debouncing, Shift-and-Add Multiplier Array Multiplier, A Signed Integer/Fraction Multiplier, (Excluding Test Bench) , Keypad Scanner (Excluding Test Bench)

SM Charts and Microprogramming: State Machine Charts, Derivation of SM Charts, SM chart for binary multiplier , Dice Game (Excluding Test Bench) , Realization of SM Charts , Implementation of the Dice Game . Microprogramming , Linked State Machines.

Floating-Point Arithmetic: Representation of Floating-Point Numbers, Floating-Point Multiplication, Floating-Point Addition, Other Floating-Point Operations. Multivalued Logic and Signal Resolution, Built-in Primitives, User-Defined Primitives, SRAM Model, Rise and Fall Delays of Gates, Rise and Fall Delays of Gates

Designing with Field Programmable Gate Arrays: Implementing Functions in FPGAs, Implementing Functions Using Shannon’s Decomposition Carry Chains in FPGAs , Cascade Chains in FPGAs , Examples of Logic Blocks in Commercial FPGAs , Examples of Logic Blocks in Commercial FPGAs, Dedicated Multipliers in FPGAs, FPGAs
Capacity: Maximum gates versus Usable gates , Design Translation.

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