Overview of Digital Design with Verilog HDL: Evolution of Computer-Aided Digital Design (CAD), Emergence of HDLs, Typical Design flow, Importance of HDLs, Popularity of Verilog HDL, Trends in HDLs.

Hierarchical Modeling Concepts: Design Methodologies, Top-down and Bottom-up design methodology, Modules, Instances, Components of a Simulation, Design Block, Stimulus Block (Test Bench) with example.

Basic Concepts: Lexical Conventions, Data Types, System Tasks, Compiler Directives.

Modules and Ports: Modules, Ports, Connecting Ports, Hierarchical Names.

Gate-Level Modeling: Gate Types-Modeling using basic Verilog gate primitives, Description of AND/OR and BUF/NOT type gates. Gate Delays-Rise, Fall and Turn-Off Delays, Min, Max and Typical Delays.

Dataflow Modeling: Continuous assignments, Delay Specification, Expressions, Operators, Operands, Operator Types, Examples

Behavioral Description: Structured Procedures, Initial and Always statements, Procedural Assignments Blocking and Non-Blocking statements, Conditional statements, Multiway Branching, Loops, Sequential and Parallel blocks, Examples-4-to-1 Multiplexer, 4-bit Counter.

Structural Description: Highlights of Structural Descriptions, Organization of Structural Description, Binding.

Tasks and Functions: Differences between Tasks and Functions, Declaration and Invocation, Examples.